1. Field of the Invention
The present invention relates to a zero cross detection circuit to be mounted on a semiconductor integrated circuit of a one-chip microcomputer and operated by a single power source.
2. Description of the Prior Art
FIG. 3 is an equivalent circuit diagram of a zero cross detection circuit to be operated by a single power source and using a P-channel transistor differential amplification circuit according to the prior art. In FIG. 3, numeral 1 is an input terminal, 2 is an output terminal, and 3 is a power source which is a 5-V single power source generally used for microcomputers. Numeral 4 is a grounded circuit; 5 is a P-channel transistor whose source is connected to the power source 3 and whose drain and gate are connected each other; 6 is an N-channel transistor whose gate is connected to the power source 3, whose source is connected to the ground 4, and whose drain is connected to the drain of the P-channel transistor 5; 7 is a P-channel transistor whose source is connected to the power source 3 and whose gate is connected to the gate of the P-channel transistor 5; 8 is an N-channel transistor whose source is connected to the ground 4 and whose drain and gate are connected each other; 9 is an N-channel transistor whose source is connected to the ground 4 and whose gate is connected to the gate of the N-channel transistor 8; 10 is a P-channel transistor whose one end is connected to the drain of the P-channel transistor 7, whose other end is connected to the drain of the N-channel transistor 8, and whose gate in connected to the ground 4; 11 is a P-channel transistor whose one end is connected to the drain of the N-channel transistor 9, whose other end is connected to the drain of the P-channel transistor 7, and whose gate is connected to the input terminal 1; 12 is a P-channel transistor whose source is connected to the power source 3, whose drain is connected to the output terminal 2, and whose gate is connected to the gate of the P-channel transistor 5; 13 is an N-channel transistor whose source is connected to the grounded circuit 4, whose drain is connected to the drain of the P-channel transistor 12, and whose gate is connected to the drain of the N-channel transistor 9; and 14 is a CMOS differential amplification circuit comprising the P-channel transistors 7, 10, and 11, and the N-channel transistors 8 and 9.
The following is the description of operations of the circuit. The potential of the point A becomes a function of threshold potential of the P-channel transistor 5 and N-channel transistor 6 and is kept constant because the gate and drain of the P-channel transistor 5 are connected each other.
The P-channel transistor 7 serves as a constant current source because the gate potential is fixed to the potential of the point A. Resultingly, the potential of the point B is kept approximately constant.
The N-channel transistors 8 and 9 constitute a current mirror circuit, which operate so that the current of the P-channel transistor 10 will be equal to that of the P-channel transistor 11 and increase the voltage gain at this stage.
The above circuit constitution causes two actions to work on the point C in accordance with the potential change of the input terminal 1. When the potential of the input terminal 1 exceeds the potential (zero volt which is hereafter referred to as ground potential) of the ground 4, the potential difference between both ends of the P-channel transistor 11 increases as the first action to decrease the potential of the point C. As the second action, the potential of the point D increases by the value equivalent to the potential change of the point C but the N-channel transistor 8 decreases the potential of the point D. The N-channel transistors 8 and 9 are designed so that they have the same characteristic and the gate terminals of the them are connected each other. Therefore, the N-channel transistor 9 decreases the potential of the point C by the potential value of the point D decreased by the N-channel transistor 8. Thus, these two actions decrease the potential of the point C and increase the potential of the output terminal 2 through the N-channel transistor 13.
However, when the potential of the input terminal 1 decreases below the ground potential, the potential of the input terminal 2 is decreased due to actions opposite to the above actions.
Thus, it is possible to compare the potential of the input terminal 1 with the ground potential and detect the zero cross.
FIG. 4(a) shows the potential change of an input signal in the embodiment of the prior art and FIG. 4(b) shows the potential change of an output signal in the embodiment of the prior art. In FIGS. 4(a) and 4(b), L1 is an input signal , L4 is an output signal, and V1 is residual voltage.
The differential amplification circuit 14 has a residual voltage of 1 V, for example, in its circuitry, and cannot amplify a signal having a voltage less than 1 V. Therefore, the differential amplification circuit 14 cannot amplify a signal having a voltage less than 1 V when the residual voltage thereof is 1 V as shown in FIG. 4(a). Therefore, voltage equal to or lower than the residual voltage V1 cannot be amplified. Therefore, as shown in FIGS. 4(a) and 4(b), the differential amplification circuit 14 outputs the minimum output voltage when the level of the input signal L1 is equal to or lower than the residual voltage V1. When the level of the input signal L1 exceeds the residual voltage V1, the differential amplification circuit 14 recognizes that the level of the input signal L1 exceeds the ground voltage and suddenly raises the output potential.